Design of Mt-cmos Domino Logic for Ultra Low Power High Performance Ripple Carry Adder

As the requirement of low power high performance arithmetic circuits, in this paper we introduced a design of new MT-CMOS domino logic and FTL dynamic logic technique to design adder circuit. The MT-MOS transistors reduce the power dissipation by minimizing sub threshold leakage current in domino logic circuits introduced. The MT-NMOS transistor connected in discharging path of output inverter can be applied for pipeline structure to reduce the power consumptions and increase fan-out. Dynamic logic style CMOS circuit is used to improve the speed and reduce the area of design by decreasing the device count. The introduced FTL dynamic logic circuit improves the performance by evaluating the computational blocks partially before its input signals are formalized and then rapidly performs a final evaluation as soon as the inputs arrive. This dynamic logic formation is well suited for arithmetic circuits where the critical path is made of a large cascade of inverting gates. The combination of MT-CMOS and dynamic logic circuit provides high fan-out, high switching frequencies since both lower delay and dynamic power consumption. The simulation results of these proposed low power high performance circuits are provides 75% of power reduction, 3 times increased high speed operation and active area minimization, while revealing lower sensitivity to power supply, temperature, capacitive load and process variations than the dynamic domino CMOS technologies.